36 lines
936 B
Python
36 lines
936 B
Python
from nmigen import *
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from nmigen.back import rtlil, verilog, pysim
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class Counter(Elaboratable):
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def __init__(self, width):
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self.v = Signal(width, reset=2**width-1)
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self.o = Signal()
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self.en = Signal()
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def elaborate(self, platform):
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m = Module()
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m.d.sync += self.v.eq(self.v + 1)
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m.d.comb += self.o.eq(self.v[-1])
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return EnableInserter(self.en)(m)
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ctr = Counter(width=16)
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print(verilog.convert(ctr, ports=[ctr.o, ctr.en]))
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with pysim.Simulator(ctr,
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vcd_file=open("ctrl.vcd", "w"),
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gtkw_file=open("ctrl.gtkw", "w"),
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traces=[ctr.en, ctr.v, ctr.o]) as sim:
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sim.add_clock(1e-6)
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def ce_proc():
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yield; yield; yield
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yield ctr.en.eq(1)
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yield; yield; yield
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yield ctr.en.eq(0)
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yield; yield; yield
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yield ctr.en.eq(1)
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sim.add_sync_process(ce_proc())
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sim.run_until(100e-6, run_passive=True)
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