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back.pysim: new simulator backend (WIP).

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This commit is contained in:
whitequark 2018-12-13 18:00:05 +00:00
parent 71f1f717c4
commit fb27c2520b
9 changed files with 437 additions and 17 deletions
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4
nmigen/test/test_fhdl_dsl.py
View file

@ -116,7 +116,7 @@ class DSLTestCase(FHDLTestCase):
(
(switch (cat (sig s1) (sig s2))
(case -1 (eq (sig c1) (const 1'd1)))
(case 1- (eq (sig c2) (const 0'd0)))
(case 1- (eq (sig c2) (const 1'd0)))
)
)
""")
@ -134,7 +134,7 @@ class DSLTestCase(FHDLTestCase):
(
(switch (cat (sig s1) (sig s2))
(case -1 (eq (sig c1) (const 1'd1)))
(case 1- (eq (sig c2) (const 0'd0)))
(case 1- (eq (sig c2) (const 1'd0)))
(case -- (eq (sig c3) (const 1'd1)))
)
)

15
nmigen/test/test_fhdl_value.py
View file

@ -59,10 +59,10 @@ class ValueTestCase(FHDLTestCase):
class ConstTestCase(FHDLTestCase):
def test_shape(self):
self.assertEqual(Const(0).shape(), (0, False))
self.assertEqual(Const(0).shape(), (1, False))
self.assertEqual(Const(1).shape(), (1, False))
self.assertEqual(Const(10).shape(), (4, False))
self.assertEqual(Const(-10).shape(), (4, True))
self.assertEqual(Const(-10).shape(), (5, True))
self.assertEqual(Const(1, 4).shape(), (4, False))
self.assertEqual(Const(1, (4, True)).shape(), (4, True))
@ -70,12 +70,15 @@ class ConstTestCase(FHDLTestCase):
with self.assertRaises(TypeError):
Const(1, -1)
def test_normalization(self):
self.assertEqual(Const(0b10110, (5, True)).value, -10)
def test_value(self):
self.assertEqual(Const(10).value, 10)
def test_repr(self):
self.assertEqual(repr(Const(10)), "(const 4'd10)")
self.assertEqual(repr(Const(-10)), "(const 4'sd-10)")
self.assertEqual(repr(Const(-10)), "(const 5'sd-10)")
def test_hash(self):
with self.assertRaises(TypeError):
@ -205,7 +208,7 @@ class OperatorTestCase(FHDLTestCase):
def test_mux(self):
s = Const(0)
v1 = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
self.assertEqual(repr(v1), "(m (const 0'd0) (const 4'd0) (const 6'd0))")
self.assertEqual(repr(v1), "(m (const 1'd0) (const 4'd0) (const 6'd0))")
self.assertEqual(v1.shape(), (6, False))
v2 = Mux(s, Const(0, (4, True)), Const(0, (6, True)))
self.assertEqual(v2.shape(), (6, True))
@ -216,7 +219,7 @@ class OperatorTestCase(FHDLTestCase):
def test_bool(self):
v = Const(0).bool()
self.assertEqual(repr(v), "(b (const 0'd0))")
self.assertEqual(repr(v), "(b (const 1'd0))")
self.assertEqual(v.shape(), (1, False))
def test_hash(self):
@ -243,7 +246,7 @@ class CatTestCase(FHDLTestCase):
c2 = Cat(Const(10), Const(1))
self.assertEqual(c2.shape(), (5, False))
c3 = Cat(Const(10), Const(1), Const(0))
self.assertEqual(c3.shape(), (5, False))
self.assertEqual(c3.shape(), (6, False))
def test_repr(self):
c1 = Cat(Const(10), Const(1))

10
nmigen/test/test_fhdl_xfrm.py
View file

@ -32,7 +32,7 @@ class DomainRenamerTestCase(FHDLTestCase):
(
(eq (sig s1) (clk pix))
(eq (rst pix) (sig s2))
(eq (sig s3) (const 0'd0))
(eq (sig s3) (const 1'd0))
(eq (sig s4) (clk other))
(eq (sig s5) (rst other))
)
@ -127,7 +127,7 @@ class ResetInserterTestCase(FHDLTestCase):
self.assertRepr(f.statements, """
(
(eq (sig s1) (const 1'd1))
(eq (sig s2) (const 0'd0))
(eq (sig s2) (const 1'd0))
(switch (sig c1)
(case 1 (eq (sig s2) (const 1'd1)))
)
@ -144,7 +144,7 @@ class ResetInserterTestCase(FHDLTestCase):
f = ResetInserter(self.c1)(f)
self.assertRepr(f.statements, """
(
(eq (sig s2) (const 0'd0))
(eq (sig s2) (const 1'd0))
(switch (sig c1)
(case 1 (eq (sig s2) (const 1'd1)))
)
@ -161,7 +161,7 @@ class ResetInserterTestCase(FHDLTestCase):
f = ResetInserter(self.c1)(f)
self.assertRepr(f.statements, """
(
(eq (sig s3) (const 0'd0))
(eq (sig s3) (const 1'd0))
(switch (sig c1)
(case 1 )
)
@ -206,7 +206,7 @@ class CEInserterTestCase(FHDLTestCase):
self.assertRepr(f.statements, """
(
(eq (sig s1) (const 1'd1))
(eq (sig s2) (const 0'd0))
(eq (sig s2) (const 1'd0))
(switch (sig c1)
(case 0 (eq (sig s2) (sig s2)))
)