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fhdl.ir: remove iter_domains().

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whitequark 2018-12-13 10:18:57 +00:00
parent f4340c19bb
commit fde2471963
3 changed files with 5 additions and 9 deletions
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2
nmigen/back/rtlil.py
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@ -480,7 +480,7 @@ def convert_fragment(builder, fragment, name, top, clock_domains):
# however, differs between domains: for comb domains, it is `always`, for sync domains
# with sync reset, it is `posedge clk`, for sync domains with async rest it is
# `posedge clk or posedge rst`.
for domain, signals in fragment.iter_domains():
for domain, signals in fragment.drivers.items():
triggers = []
if domain is None:
triggers.append(("always",))

3
nmigen/fhdl/ir.py
View file

@ -25,9 +25,6 @@ class Fragment:
self.drivers[domain] = ValueSet()
self.drivers[domain].add(signal)
def iter_domains(self):
yield from self.drivers.items()
def iter_drivers(self):
for domain, signals in self.drivers.items():
for signal in signals:

9
nmigen/fhdl/xfrm.py
View file

@ -102,9 +102,8 @@ class FragmentTransformer:
new_fragment.add_statements(fragment.statements)
def map_drivers(self, fragment, new_fragment):
for domain, signals in fragment.iter_domains():
for signal in signals:
new_fragment.drive(signal, domain)
for domain, signal in fragment.iter_drivers():
new_fragment.drive(signal, domain)
def on_fragment(self, fragment):
new_fragment = Fragment()
@ -134,7 +133,7 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
return value
def map_drivers(self, fragment, new_fragment):
for domain, signals in fragment.iter_domains():
for domain, signals in fragment.drivers.items():
if domain in self.domains:
domain = self.domains[domain]
for signal in signals:
@ -149,7 +148,7 @@ class _ControlInserter(FragmentTransformer):
def on_fragment(self, fragment):
new_fragment = super().on_fragment(fragment)
for domain, signals in fragment.iter_domains():
for domain, signals in fragment.drivers.items():
if domain is None or domain not in self.controls:
continue
self._insert_control(new_fragment, domain, signals)