usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

lib.cdc: add tests for MultiReg.

Browse source
This commit is contained in:
whitequark 2018-12-26 12:58:30 +00:00
parent 35a44f017f
commit fe8cb55204
2 changed files with 44 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

40
nmigen/test/test_lib_cdc.py Normal file
View file

@ -0,0 +1,40 @@
from .tools import *
from ..hdl.ast import *
from ..back.pysim import *
from ..lib.cdc import *
class MultiRegTestCase(FHDLTestCase):
def test_basic(self):
i = Signal()
o = Signal()
frag = MultiReg(i, o)
with Simulator(frag) as sim:
sim.add_clock(1e-6)
def process():
self.assertEqual((yield o), 0)
yield i.eq(1)
yield Tick()
self.assertEqual((yield o), 0)
yield Tick()
self.assertEqual((yield o), 0)
yield Tick()
self.assertEqual((yield o), 1)
sim.add_process(process)
def test_basic(self):
i = Signal(reset=1)
o = Signal()
frag = MultiReg(i, o, reset=1)
with Simulator(frag) as sim:
sim.add_clock(1e-6)
def process():
self.assertEqual((yield o), 1)
yield i.eq(0)
yield Tick()
self.assertEqual((yield o), 1)
yield Tick()
self.assertEqual((yield o), 1)
yield Tick()
self.assertEqual((yield o), 0)
sim.add_process(process)