whitequark
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a061bfaa6c
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hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
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2b4a8510ca
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back.rtlil: implement memories.
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2018-12-21 01:55:59 +00:00 |
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whitequark
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ac498414ab
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back.verilog: remove debug code.
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2018-12-13 13:42:54 +00:00 |
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whitequark
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6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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4e32f6b8de
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back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
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2018-12-13 04:59:48 +00:00 |
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whitequark
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4d3258013d
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Initial commit.
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2018-12-12 03:18:44 +00:00 |
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