whitequark
94e8f479a5
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
...
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).
Fixes #116 .
2019-07-01 19:56:49 +00:00
whitequark
44711b7d08
hdl.ir: detect elaboratables that are created but not used.
...
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3 .
2019-04-21 08:52:57 +00:00
whitequark
4027317835
lib.fifo: register GrayEncoder output before CDC.
...
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.
Reported by @Wren6991.
2019-03-03 18:23:51 +00:00
whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
...
Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
7b25665fde
back.pysim: fix behavior of initial cycle for sync processes.
...
The current behavior was introduced in 6570271912e04e4e657027191782b841
2019-01-25 20:37:56 +00:00
whitequark
1782b841b2
lib.fifo: in FIFOInterface.read(), check readable on the right cycle.
2019-01-22 07:03:46 +00:00
whitequark
2c80f35de4
lib.fifo: fix typo in AsyncFIFO documentation.
2019-01-22 05:47:50 +00:00
whitequark
e33580cf4c
lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
2019-01-21 16:02:46 +00:00
whitequark
3ed519383c
lib.fifo: fix simulation read/write methods to take only one cycle.
2019-01-19 01:38:09 +00:00
whitequark
97b990272e
lib.fifo: formally verify FIFO contract.
2019-01-19 00:52:56 +00:00
whitequark
5a831ce31c
lib.fifo: add basic formal specification.
2019-01-17 05:40:25 +00:00
whitequark
b78a2be9f6
lib.fifo: port sync FIFO queues from Migen.
2019-01-16 17:20:38 +00:00
