whitequark
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286a8009c8
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compat.fhdl: reexport Array.
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2018-12-16 10:39:54 +00:00 |
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whitequark
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d4e8d3e95a
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back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
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2018-12-16 10:31:42 +00:00 |
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whitequark
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d9579219ee
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test.sim: generalize assertOperator. NFC.
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2018-12-15 21:08:29 +00:00 |
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whitequark
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bdb8db2826
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back.pysim: add (stub) LHSValueCompiler.
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2018-12-15 21:01:38 +00:00 |
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whitequark
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20a04bca88
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back.pysim: implement Part.
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2018-12-15 20:58:06 +00:00 |
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whitequark
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1adf58f561
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examples: rename clkdiv/ctrl to ctr/ctr_ce.
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2018-12-15 20:42:52 +00:00 |
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whitequark
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6c601fecfa
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doc: update COMPAT_SUMMARY.
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2018-12-15 20:40:56 +00:00 |
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whitequark
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54fb999c99
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back.pysim: implement ArrayProxy.
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2018-12-15 19:37:36 +00:00 |
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whitequark
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80c5343600
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hdl.ast: implement Array and ArrayProxy.
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2018-12-15 17:16:31 +00:00 |
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whitequark
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1580b6e542
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Lower Python version requirement to 3.6.
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2018-12-15 17:03:23 +00:00 |
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whitequark
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c6e7a93717
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hdl: appropriately rename tests. NFC.
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2018-12-15 16:13:53 +00:00 |
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whitequark
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f603b735e8
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hdl.ast: improve ClockSignal, ResetSignal documentation.
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2018-12-15 14:58:31 +00:00 |
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whitequark
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790eb05a92
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Rename fhdl→hdl, genlib→lib.
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2018-12-15 14:25:31 +00:00 |
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whitequark
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b5a1efa0c8
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Move star imports to make from nmigen import * usable.
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2018-12-15 14:20:10 +00:00 |
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whitequark
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ad3c88852f
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doc: fix some Markdown awkwardness.
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2018-12-15 12:07:56 +00:00 |
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whitequark
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cc96a7ecfa
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doc: update COMPAT_SUMMARY to reflect actual status.
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2018-12-15 12:04:52 +00:00 |
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whitequark
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1f10bd96b9
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Determine Migen's API surface and document compatibility summary.
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
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2018-12-15 11:52:30 +00:00 |
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whitequark
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b70340c0da
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pyback.sim: test Slice, Cat, Repl.
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2018-12-15 10:09:14 +00:00 |
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whitequark
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db4600d52b
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fhdl.ast, back.pysim: implement shifts.
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2018-12-15 09:58:30 +00:00 |
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whitequark
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46f5addf05
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fhdl.ast: refactor Operator.shape(). NFC.
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2018-12-15 09:46:20 +00:00 |
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whitequark
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3a8685c352
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Consistently use '{!r}' in and only in TypeError messages.
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2018-12-15 09:31:58 +00:00 |
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whitequark
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f9f7921959
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fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
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2018-12-15 09:26:36 +00:00 |
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whitequark
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f5e8c9033d
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fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
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2018-12-15 09:26:23 +00:00 |
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whitequark
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9010805040
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compat.fhdl.structure: handle If/Elif with multi-bit condition.
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2018-12-15 00:10:54 +00:00 |
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whitequark
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ecea721f43
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compat.fhdl.module: allow adding native submodules to compat modules.
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2018-12-14 23:56:50 +00:00 |
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whitequark
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1c7b43ea49
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Fix deprecations in Python 3.7.
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2018-12-14 23:56:50 +00:00 |
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whitequark
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7108111ad0
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back.pysim: preserve process locations through add_sync_process().
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2018-12-14 23:27:36 +00:00 |
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whitequark
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c4ba5a3915
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fhdl.ast: clean up stub error messages. NFC.
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2018-12-14 23:07:16 +00:00 |
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whitequark
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2001359b66
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fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
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2018-12-14 22:48:17 +00:00 |
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whitequark
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579feaba4e
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fhdl.ir: Fragment.{drive→add_driver}
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2018-12-14 20:58:29 +00:00 |
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whitequark
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0015713bfb
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back.pysim: count delta cycles separately to avoid clock drift.
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2018-12-14 20:52:41 +00:00 |
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whitequark
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a6a8703a0e
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back.pysim: simplify.
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2018-12-14 20:45:45 +00:00 |
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whitequark
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7e3cf26cf8
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back.pysim: revert 70ebc6f2.
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2018-12-14 19:46:08 +00:00 |
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whitequark
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71304c9fe7
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back.pysim: fix implicit boolean conversion.
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2018-12-14 19:08:06 +00:00 |
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whitequark
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fe5fb34fae
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back.pysim: squash one level of hierarchy.
There's really no point in the "top" node.
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2018-12-14 18:53:21 +00:00 |
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whitequark
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70ebc6f2c1
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back.pysim: implement blocking assignment semantics correctly.
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2018-12-14 18:47:12 +00:00 |
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whitequark
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120d817123
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back.pysim: undriven sync signals should return to previous value.
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2018-12-14 17:25:48 +00:00 |
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whitequark
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4f5b4a9bf4
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back.pysim: in simulator sync processes, start by waiting for a tick.
This matches Migen behavior and also makes more sense.
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2018-12-14 17:05:11 +00:00 |
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whitequark
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e230383aac
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back.pysim: make initial phase configurable.
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2018-12-14 16:46:16 +00:00 |
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whitequark
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0ef5ced492
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compat.sim: match clock period.
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2018-12-14 16:39:52 +00:00 |
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whitequark
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17d26c8329
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compat: add run_simulation shim.
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2018-12-14 16:22:18 +00:00 |
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whitequark
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88970ee29f
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pysim.back: fix add_sync_process wrapper to handle signals correctly.
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2018-12-14 16:21:53 +00:00 |
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whitequark
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3bc3647380
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compat.fhdl.module: fix specials.
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2018-12-14 16:14:08 +00:00 |
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whitequark
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3b23645fb7
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compat: add fhdl.specials.TSTriple shim.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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7200346249
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genlib.io: import TSTriple from Migen.
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2018-12-14 16:09:51 +00:00 |
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whitequark
|
50ba443f92
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fhdl.ast: fix Switch with constant test.
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2018-12-14 16:09:51 +00:00 |
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whitequark
|
a0d555a9fc
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compat: add genlib.cdc.MultiReg shim.
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2018-12-14 16:01:38 +00:00 |
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whitequark
|
baba47251c
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compat.fhdl.module: update deprecation messages.
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2018-12-14 16:01:38 +00:00 |
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whitequark
|
9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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whitequark
|
e3f32a1faf
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back.pysim: better naming. NFC.
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2018-12-14 15:21:13 +00:00 |
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