whitequark
94e8f479a5
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
...
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).
Fixes #116 .
2019-07-01 19:56:49 +00:00
whitequark
58e39f90ce
hdl.mem: coerce memory init values to integers.
...
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.
Fixes #93 .
2019-06-11 03:38:44 +00:00
whitequark
44711b7d08
hdl.ir: detect elaboratables that are created but not used.
...
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3 .
2019-04-21 08:52:57 +00:00
whitequark
e93bf4bf4b
tracer: factor out get_var_name(default=).
2019-03-03 18:21:22 +00:00
whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
...
Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
d66bbb0df8
tracer: factor out get_src_loc().
2018-12-28 01:31:24 +00:00
whitequark
de50ccec90
hdl.mem: add missing __all__.
2018-12-27 16:19:01 +00:00
whitequark
f05bd2a137
hdl.mem: allow omitting memory simulation logic.
...
Trying to transform very large arrays is slow.
2018-12-24 11:53:59 +00:00
whitequark
8730895d8c
hdl.mem: allow changing init value after creating memory.
2018-12-22 01:09:03 +00:00
whitequark
a4183eba69
hdl.mem: use more informative signal naming for ports.
2018-12-21 23:55:02 +00:00
whitequark
fa2af27bb0
hdl.mem: ensure transparent read port model has correct latency.
2018-12-21 13:01:08 +00:00
whitequark
af7db882c0
hdl.mem: use different naming for array signals.
...
It looks like [] is confusing gtkwave somehow.
2018-12-21 12:26:49 +00:00
whitequark
e58d9ec74d
hdl.mem: add simulation model for memory.
2018-12-21 11:54:32 +00:00
whitequark
c49211c76a
hdl.mem: add tests for all error conditions.
2018-12-21 06:07:16 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
6d9a6b5d84
hdl.mem: implement memories.
2018-12-21 01:53:32 +00:00
