Commit graph

25 commits

Author SHA1 Message Date
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests 2021-01-06 01:05:46 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary.
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
2020-12-12 12:42:12 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape().
This method was lost in commit abbebf8e.
2020-11-17 19:36:58 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand.
Otherwise it behaves funny when it's eg. the result of operator ~.
2020-11-14 15:22:34 +00:00
whitequark d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.
This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.
2020-11-10 05:30:30 +00:00
awygle ea94c9cc45
hdl.rec: proxy operators correctly.
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
2020-11-09 20:20:25 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable.
Closes #527.
2020-11-06 02:21:53 +00:00
whitequark 10fd5cff4b CI: run testsuite with -Werror. 2020-11-06 01:38:03 +00:00
awygle abbebf8efe
hdl.rec: migrate Record from UserValue to ValueCastable.
Closes #528.
2020-11-06 01:10:39 +00:00
awygle 06c734992f
hdl.ast: implement ValueCastable.
Closes RFC issue #355.
2020-11-06 00:20:54 +00:00
Jaro Habiger b15f0562a6 lib.fifo: fix {r,w}_level in AsyncFIFOBuffered 2020-11-03 09:34:12 +00:00
Jaro Habiger c7014f84ea lib.fifo: fix level on fifo full 2020-11-03 09:20:30 +00:00
Robin Ole Heinemann 05decc43b2 lib.fifo.AsyncFFSynchronizer: check input and output signal width 2020-10-28 00:08:38 +00:00
whitequark e3207b74f4 build.dsl: clean up inversion logic.
* Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.
2020-10-26 19:50:21 +00:00
anuejn d8273a15c3
lib.fifo.AsyncFIFO: fix incorrect latency of r_level.
Co-authored-by: Andrew Wygle <awygle@gmail.com>
2020-10-24 14:58:23 +00:00
anuejn ca6fa036f6
tests: make spec directory name unique per test method. 2020-10-22 21:38:44 +00:00
whitequark df70aae887 sim._pyrtl: sign extend RHS of assignment.
Fixes #502.
2020-10-22 16:08:38 +00:00
whitequark 9d62cbefa5 hdl.dsl: error on Elif immediately nested in an If.
I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.
2020-10-22 13:23:06 +00:00
Xiretza eb152da59b hdl.ir: Update error message for Instance arguments
48d4ee4 added the option to specify attributes using Instance arguments,
but the error message wasn't updated accordingly.
2020-10-18 23:55:46 +00:00
whitequark e58233b441 tests: keep comments up to date. NFC. 2020-10-15 17:02:50 +00:00
whitequark b65e11f38f sim: split into base, core, and engines.
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
2020-08-27 11:52:31 +00:00
whitequark 4180cc537b _toolchain.cxx: new toolchain. 2020-08-27 06:39:00 +00:00
whitequark fde242aa47 hdl.ast: clarify exception message for out of bounds indexing.
Fixes #488.
2020-08-27 01:14:05 +00:00
whitequark 67b957d4f4 tests: move out of the main package.
Compared to tests in the repository root, tests in the package have
many downsides:
  * Unless explicitly excluded in find_packages(), tests and their
    support code effectively become a part of public API.
    This, unfortunately, happened with FHDLTestCase, which was never
    intended for downstream use.
  * Even if explicitly excluded from the setuptools package, using
    an editable install, or setting PYTHONPATH still allows accessing
    the tests.
  * Having a sub-package that is present in the source tree but not
    exported (or, worse, exported only sometimes) is confusing.
  * The name `nmigen.test` cannot be used for anything else, such as
    testing utilities that *are* intended for downstream use.
2020-08-27 00:33:31 +00:00