whitequark
015998eba9
hdl.dsl: add clock domain support.
2018-12-16 23:51:24 +00:00
whitequark
b2f828387a
hdl.dsl: cleanup. NFC.
2018-12-16 23:44:00 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
80c5343600
hdl.ast: implement Array and ArrayProxy.
2018-12-15 17:16:31 +00:00
whitequark
f603b735e8
hdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 14:58:31 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
