whitequark
|
3d04122d55
|
examples: reorganize into examples/basic and examples/board.
|
2019-06-03 16:17:37 +00:00 |
|
|
whitequark
|
44711b7d08
|
hdl.ir: detect elaboratables that are created but not used.
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3.
|
2019-04-21 08:52:57 +00:00 |
|
|
whitequark
|
4948162f33
|
hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
|
2019-01-26 02:31:12 +00:00 |
|
|
whitequark
|
cf79738744
|
cli: new module, for basic design generaton/simulation.
|
2018-12-23 00:06:58 +00:00 |
|
|
whitequark
|
a061bfaa6c
|
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
|
2018-12-21 04:22:16 +00:00 |
|
|
whitequark
|
2b4a8510ca
|
back.rtlil: implement memories.
|
2018-12-21 01:55:59 +00:00 |
|