4 commits

Author	SHA1	Message	Date
whitequark	4948162f33	hdl.ir: rename .get_fragment() to .elaborate(). ... Closes #9.	2019-01-26 02:31:12 +00:00
whitequark	cf79738744	cli: new module, for basic design generaton/simulation.	2018-12-23 00:06:58 +00:00
whitequark	a061bfaa6c	hdl.mem: tie rdport.en high for asynchronous or transparent ports.	2018-12-21 04:22:16 +00:00
whitequark	2b4a8510ca	back.rtlil: implement memories.	2018-12-21 01:55:59 +00:00