whitequark
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4948162f33
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hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
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2019-01-26 02:31:12 +00:00 |
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whitequark
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d78e6c155b
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hdl.mem: add DummyPort, for testing and verification.
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2019-01-01 03:08:10 +00:00 |
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whitequark
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d66bbb0df8
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tracer: factor out get_src_loc().
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2018-12-28 01:31:24 +00:00 |
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whitequark
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de50ccec90
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hdl.mem: add missing __all__.
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2018-12-27 16:19:01 +00:00 |
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whitequark
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f05bd2a137
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hdl.mem: allow omitting memory simulation logic.
Trying to transform very large arrays is slow.
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2018-12-24 11:53:59 +00:00 |
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whitequark
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8730895d8c
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hdl.mem: allow changing init value after creating memory.
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2018-12-22 01:09:03 +00:00 |
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whitequark
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a4183eba69
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hdl.mem: use more informative signal naming for ports.
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2018-12-21 23:55:02 +00:00 |
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whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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af7db882c0
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hdl.mem: use different naming for array signals.
It looks like [] is confusing gtkwave somehow.
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2018-12-21 12:26:49 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
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a061bfaa6c
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hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
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6d9a6b5d84
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hdl.mem: implement memories.
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2018-12-21 01:53:32 +00:00 |
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