6 commits

Author	SHA1	Message	Date
Jacob Lifshay	995f3a147b	Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation ... Fixes #344	2020-04-02 02:46:44 +00:00
whitequark	a2241fcfdb	back.{rtlil,verilog}: split convert_fragment() off convert(). ... Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.	2019-08-19 19:49:51 +00:00
whitequark	fdb0c5a6bc	hdl.ir: call back from Fragment.prepare if a clock domain is missing. ... See #57.	2019-08-03 14:54:20 +00:00
whitequark	7890c0adc8	test.compat: reenable tests converting to Verilog.	2019-01-26 15:29:09 +00:00
whitequark	4948162f33	hdl.ir: rename .get_fragment() to .elaborate(). ... Closes #9.	2019-01-26 02:31:12 +00:00
whitequark	00ef7a78d3	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00