8 commits

Author	SHA1	Message	Date
whitequark	913339c04a	hdl.ir: fix port propagation between siblings.	2018-12-21 23:53:18 +00:00
whitequark	fc7da1be2d	hdl.ir: do not flatten instances or collect ports from their statements. ... This results in absurd behavior for memories.	2018-12-21 13:52:18 +00:00
whitequark	b0bd7bfaca	hdl.ir: correctly handle named output and inout ports.	2018-12-21 04:03:03 +00:00
whitequark	f7fec804ec	ir: allow non-Signals in Instance ports.	2018-12-20 23:40:40 +00:00
whitequark	c7f9386eab	fhdl.ir: add black-box fragments, fragment parameters, and Instance.	2018-12-17 22:55:39 +00:00
whitequark	8d1639a5a8	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
whitequark	015998eba9	hdl.dsl: add clock domain support.	2018-12-16 23:51:24 +00:00
whitequark	790eb05a92	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00

Renamed from nmigen/fhdl/ir.py (Browse further)