Commit graph

6 commits

Author SHA1 Message Date
whitequark 9bdb7accc8 sim.pysim: in write_vcd(), close files if an exception is raised.
This also avoids leaving the waveform writer list in an inconsistent
state after an exception.
2020-08-27 08:34:18 +00:00
whitequark 9bc42cb8c5 sim._pyclock: new type of process.
The overhead of coroutine processes is fairly high. A clock driver
implemented through a coroutine process is mostly overhead. This was
partially addressed in commit 2398b792 by microoptimizing yielding.

This commit eliminates the coroutine process overhead completely by
introducing dedicated clock processes. It also simplifies the logic
to a simple toggle.

This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 07:56:47 +00:00
Jacob Lifshay 58f1d4bcb6
sim.pysim: write the next, not curr signal value to the VCD file
This is a temporary fix for #429.
2020-07-13 02:10:01 +00:00
whitequark 0a90aa1b17 sim.pysim: use VCD aliases to reduce space and time overhead.
On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.
2020-07-11 12:26:34 +00:00
whitequark 30e2f91176 sim: simplify. NFC. 2020-07-08 17:31:53 +00:00
whitequark d7a87fef42 back.pysim→sim.pysim; split into more manageable parts.
This is necessary to add cxxrtl as an alternate simulation engine.
2020-07-08 12:49:38 +00:00