9bc42cb8c5
The overhead of coroutine processes is fairly high. A clock driver
implemented through a coroutine process is mostly overhead. This was
partially addressed in commit 2398b792 by microoptimizing yielding.
This commit eliminates the coroutine process overhead completely by
introducing dedicated clock processes. It also simplifies the logic
to a simple toggle.
This change improves runtime by about 12% on Minerva SRAM SoC.
412 lines
15 KiB
Python
412 lines
15 KiB
Python
from contextlib import contextmanager
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import itertools
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import inspect
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from vcd import VCDWriter
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from vcd.gtkw import GTKWSave
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from .._utils import deprecated
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from ..hdl import *
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from ..hdl.ast import SignalDict
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from ._cmds import *
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from ._core import *
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from ._pyrtl import _FragmentCompiler
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from ._pycoro import PyCoroProcess
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from ._pyclock import PyClockProcess
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__all__ = ["Settle", "Delay", "Tick", "Passive", "Active", "Simulator"]
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class _NameExtractor:
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def __init__(self):
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self.names = SignalDict()
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def __call__(self, fragment, *, hierarchy=("top",)):
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def add_signal_name(signal):
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hierarchical_signal_name = (*hierarchy, signal.name)
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if signal not in self.names:
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self.names[signal] = {hierarchical_signal_name}
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else:
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self.names[signal].add(hierarchical_signal_name)
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for domain_name, domain_signals in fragment.drivers.items():
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if domain_name is not None:
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domain = fragment.domains[domain_name]
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add_signal_name(domain.clk)
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if domain.rst is not None:
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add_signal_name(domain.rst)
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for statement in fragment.statements:
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for signal in statement._lhs_signals() | statement._rhs_signals():
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if not isinstance(signal, (ClockSignal, ResetSignal)):
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add_signal_name(signal)
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for subfragment_index, (subfragment, subfragment_name) in enumerate(fragment.subfragments):
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if subfragment_name is None:
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subfragment_name = "U${}".format(subfragment_index)
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self(subfragment, hierarchy=(*hierarchy, subfragment_name))
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return self.names
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class _WaveformWriter:
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def update(self, timestamp, signal, value):
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raise NotImplementedError # :nocov:
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def close(self, timestamp):
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raise NotImplementedError # :nocov:
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class _VCDWaveformWriter(_WaveformWriter):
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@staticmethod
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def timestamp_to_vcd(timestamp):
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return timestamp * (10 ** 10) # 1/(100 ps)
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@staticmethod
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def decode_to_vcd(signal, value):
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return signal.decoder(value).expandtabs().replace(" ", "_")
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def __init__(self, fragment, *, vcd_file, gtkw_file=None, traces=()):
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if isinstance(vcd_file, str):
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vcd_file = open(vcd_file, "wt")
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if isinstance(gtkw_file, str):
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gtkw_file = open(gtkw_file, "wt")
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self.vcd_vars = SignalDict()
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self.vcd_file = vcd_file
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self.vcd_writer = vcd_file and VCDWriter(self.vcd_file,
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timescale="100 ps", comment="Generated by nMigen")
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self.gtkw_names = SignalDict()
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self.gtkw_file = gtkw_file
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self.gtkw_save = gtkw_file and GTKWSave(self.gtkw_file)
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self.traces = []
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signal_names = _NameExtractor()(fragment)
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trace_names = SignalDict()
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for trace in traces:
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if trace not in signal_names:
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trace_names[trace] = {("top", trace.name)}
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self.traces.append(trace)
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if self.vcd_writer is None:
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return
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for signal, names in itertools.chain(signal_names.items(), trace_names.items()):
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if signal.decoder:
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var_type = "string"
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var_size = 1
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var_init = self.decode_to_vcd(signal, signal.reset)
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else:
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var_type = "wire"
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var_size = signal.width
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var_init = signal.reset
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for (*var_scope, var_name) in names:
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suffix = None
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while True:
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try:
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if suffix is None:
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var_name_suffix = var_name
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else:
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var_name_suffix = "{}${}".format(var_name, suffix)
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if signal not in self.vcd_vars:
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vcd_var = self.vcd_writer.register_var(
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scope=var_scope, name=var_name_suffix,
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var_type=var_type, size=var_size, init=var_init)
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self.vcd_vars[signal] = vcd_var
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else:
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self.vcd_writer.register_alias(
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scope=var_scope, name=var_name_suffix,
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var=self.vcd_vars[signal])
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break
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except KeyError:
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suffix = (suffix or 0) + 1
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if signal not in self.gtkw_names:
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self.gtkw_names[signal] = (*var_scope, var_name_suffix)
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def update(self, timestamp, signal, value):
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vcd_var = self.vcd_vars.get(signal)
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if vcd_var is None:
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return
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vcd_timestamp = self.timestamp_to_vcd(timestamp)
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if signal.decoder:
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var_value = self.decode_to_vcd(signal, value)
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else:
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var_value = value
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self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
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def close(self, timestamp):
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if self.vcd_writer is not None:
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self.vcd_writer.close(self.timestamp_to_vcd(timestamp))
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if self.gtkw_save is not None:
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self.gtkw_save.dumpfile(self.vcd_file.name)
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self.gtkw_save.dumpfile_size(self.vcd_file.tell())
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self.gtkw_save.treeopen("top")
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for signal in self.traces:
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if len(signal) > 1 and not signal.decoder:
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suffix = "[{}:0]".format(len(signal) - 1)
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else:
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suffix = ""
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self.gtkw_save.trace(".".join(self.gtkw_names[signal]) + suffix)
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if self.vcd_file is not None:
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self.vcd_file.close()
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if self.gtkw_file is not None:
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self.gtkw_file.close()
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class _SignalState:
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__slots__ = ("signal", "curr", "next", "waiters", "pending")
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def __init__(self, signal, pending):
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self.signal = signal
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self.pending = pending
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self.waiters = dict()
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self.curr = self.next = signal.reset
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def set(self, value):
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if self.next == value:
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return
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self.next = value
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self.pending.add(self)
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def commit(self):
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if self.curr == self.next:
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return False
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self.curr = self.next
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awoken_any = False
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for process, trigger in self.waiters.items():
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if trigger is None or trigger == self.curr:
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process.runnable = awoken_any = True
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return awoken_any
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class _SimulatorState:
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def __init__(self):
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self.timeline = Timeline()
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self.signals = SignalDict()
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self.slots = []
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self.pending = set()
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def reset(self):
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self.timeline.reset()
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for signal, index in self.signals.items():
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self.slots[index].curr = self.slots[index].next = signal.reset
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self.pending.clear()
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def get_signal(self, signal):
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try:
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return self.signals[signal]
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except KeyError:
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index = len(self.slots)
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self.slots.append(_SignalState(signal, self.pending))
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self.signals[signal] = index
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return index
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def add_trigger(self, process, signal, *, trigger=None):
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index = self.get_signal(signal)
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assert (process not in self.slots[index].waiters or
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self.slots[index].waiters[process] == trigger)
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self.slots[index].waiters[process] = trigger
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def remove_trigger(self, process, signal):
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index = self.get_signal(signal)
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assert process in self.slots[index].waiters
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del self.slots[index].waiters[process]
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def commit(self):
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converged = True
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for signal_state in self.pending:
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if signal_state.commit():
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converged = False
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self.pending.clear()
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return converged
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class Simulator:
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def __init__(self, fragment):
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self._state = _SimulatorState()
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self._fragment = Fragment.get(fragment, platform=None).prepare()
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self._processes = _FragmentCompiler(self._state)(self._fragment)
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self._clocked = set()
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self._waveform_writers = []
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def _check_process(self, process):
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if not (inspect.isgeneratorfunction(process) or inspect.iscoroutinefunction(process)):
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raise TypeError("Cannot add a process {!r} because it is not a generator function"
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.format(process))
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return process
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def _add_coroutine_process(self, process, *, default_cmd):
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self._processes.add(PyCoroProcess(self._state, self._fragment.domains, process,
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default_cmd=default_cmd))
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def add_process(self, process):
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process = self._check_process(process)
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def wrapper():
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# Only start a bench process after comb settling, so that the reset values are correct.
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yield Settle()
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yield from process()
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self._add_coroutine_process(wrapper, default_cmd=None)
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def add_sync_process(self, process, *, domain="sync"):
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process = self._check_process(process)
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def wrapper():
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# Only start a sync process after the first clock edge (or reset edge, if the domain
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# uses an asynchronous reset). This matches the behavior of synchronous FFs.
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yield Tick(domain)
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yield from process()
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return self._add_coroutine_process(wrapper, default_cmd=Tick(domain))
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def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
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"""Add a clock process.
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Adds a process that drives the clock signal of ``domain`` at a 50% duty cycle.
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Arguments
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---------
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period : float
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Clock period. The process will toggle the ``domain`` clock signal every ``period / 2``
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seconds.
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phase : None or float
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Clock phase. The process will wait ``phase`` seconds before the first clock transition.
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If not specified, defaults to ``period / 2``.
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domain : str or ClockDomain
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Driven clock domain. If specified as a string, the domain with that name is looked up
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in the root fragment of the simulation.
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if_exists : bool
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If ``False`` (the default), raise an error if the driven domain is specified as
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a string and the root fragment does not have such a domain. If ``True``, do nothing
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in this case.
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"""
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if isinstance(domain, ClockDomain):
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pass
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elif domain in self._fragment.domains:
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domain = self._fragment.domains[domain]
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elif if_exists:
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return
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else:
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raise ValueError("Domain {!r} is not present in simulation"
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.format(domain))
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if domain in self._clocked:
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raise ValueError("Domain {!r} already has a clock driving it"
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.format(domain.name))
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if phase is None:
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# By default, delay the first edge by half period. This causes any synchronous activity
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# to happen at a non-zero time, distinguishing it from the reset values in the waveform
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# viewer.
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phase = period / 2
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self._processes.add(PyClockProcess(self._state, domain.clk, phase=phase, period=period))
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self._clocked.add(domain)
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def reset(self):
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"""Reset the simulation.
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Assign the reset value to every signal in the simulation, and restart every user process.
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"""
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self._state.reset()
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for process in self._processes:
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process.reset()
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def _real_step(self):
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"""Step the simulation.
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Run every process and commit changes until a fixed point is reached. If there is
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an unstable combinatorial loop, this function will never return.
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"""
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# Performs the two phases of a delta cycle in a loop:
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converged = False
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while not converged:
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# 1. eval: run and suspend every non-waiting process once, queueing signal changes
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for process in self._processes:
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if process.runnable:
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process.runnable = False
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process.run()
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for waveform_writer in self._waveform_writers:
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for signal_state in self._state.pending:
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waveform_writer.update(self._state.timeline.now,
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signal_state.signal, signal_state.next)
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# 2. commit: apply every queued signal change, waking up any waiting processes
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converged = self._state.commit()
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# TODO(nmigen-0.4): replace with _real_step
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@deprecated("instead of `sim.step()`, use `sim.advance()`")
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def step(self):
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return self.advance()
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def advance(self):
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"""Advance the simulation.
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Run every process and commit changes until a fixed point is reached, then advance time
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to the closest deadline (if any). If there is an unstable combinatorial loop,
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this function will never return.
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Returns ``True`` if there are any active processes, ``False`` otherwise.
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"""
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self._real_step()
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self._state.timeline.advance()
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return any(not process.passive for process in self._processes)
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def run(self):
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"""Run the simulation while any processes are active.
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Processes added with :meth:`add_process` and :meth:`add_sync_process` are initially active,
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and may change their status using the ``yield Passive()`` and ``yield Active()`` commands.
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Processes compiled from HDL and added with :meth:`add_clock` are always passive.
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"""
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while self.advance():
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pass
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def run_until(self, deadline, *, run_passive=False):
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"""Run the simulation until it advances to ``deadline``.
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If ``run_passive`` is ``False``, the simulation also stops when there are no active
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processes, similar to :meth:`run`. Otherwise, the simulation will stop only after it
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advances to or past ``deadline``.
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If the simulation stops advancing, this function will never return.
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"""
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assert self._state.timeline.now <= deadline
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while (self.advance() or run_passive) and self._state.timeline.now < deadline:
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pass
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@contextmanager
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def write_vcd(self, vcd_file, gtkw_file=None, *, traces=()):
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"""Write waveforms to a Value Change Dump file, optionally populating a GTKWave save file.
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This method returns a context manager. It can be used as: ::
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sim = Simulator(frag)
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sim.add_clock(1e-6)
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with sim.write_vcd("dump.vcd", "dump.gtkw"):
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sim.run_until(1e-3)
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Arguments
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---------
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vcd_file : str or file-like object
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Verilog Value Change Dump file or filename.
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gtkw_file : str or file-like object
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GTKWave save file or filename.
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traces : iterable of Signal
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Signals to display traces for.
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"""
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if self._state.timeline.now != 0.0:
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raise ValueError("Cannot start writing waveforms after advancing simulation time")
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waveform_writer = _VCDWaveformWriter(self._fragment,
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vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces)
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self._waveform_writers.append(waveform_writer)
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yield
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waveform_writer.close(self._state.timeline.now)
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self._waveform_writers.remove(waveform_writer)
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