whitequark
9eb81609d6
compat.fhdl.structure: fix If/Elif/Else after 32446831.
2019-07-03 13:19:15 +00:00
whitequark
32446831b4
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
...
This means that instead of:
with m.Case(0b00):
<body>
with m.Case(0b01):
<body>
it is legal to write:
with m.Case(0b00, 0b01):
<body>
with no change in semantics, and slightly nicer RTLIL or Verilog
output.
Fixes #103 .
2019-06-28 04:37:08 +00:00
whitequark
2f7e52369c
compat.fhdl.structure: fix typo.
2019-06-25 22:01:14 +00:00
whitequark
b1af0601fa
compat.fhdl.structure: simplify handling of default case.
2019-06-25 22:01:14 +00:00
whitequark
2566747061
compat.fhdl.structure: fix Case().makedefault().
...
Fixes #100 .
2019-06-13 03:56:57 +00:00
whitequark
f689b777b4
compat.fhdl.structure: always order default case as the very last.
2019-06-13 03:56:57 +00:00
whitequark
a90748303c
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
2018-12-18 20:03:32 +00:00
whitequark
db5fd1e4c4
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
2018-12-16 17:41:42 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
9010805040
compat.fhdl.structure: handle If/Elif with multi-bit condition.
2018-12-15 00:10:54 +00:00
whitequark
6251c95d4e
compat.genlib.fsm: import/wrap Migen code.
2018-12-13 12:41:19 +00:00
whitequark
b4dab74b2e
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
2018-12-12 15:47:34 +00:00
