whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
37b81309d3
back.rtlil: always initialize the entire memory.
...
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
2018-12-22 05:27:42 +00:00
whitequark
99b778158d
compat: use nicer names for next_value/next_value_ce signals.
2018-12-22 02:05:49 +00:00
whitequark
8730895d8c
hdl.mem: allow changing init value after creating memory.
2018-12-22 01:09:03 +00:00
whitequark
6ee80408bb
back.verilog: do not rename internal signals.
...
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
2018-12-22 00:53:40 +00:00
whitequark
5361b4c22b
compat: fix confusing naming for memory port address signal.
2018-12-22 00:53:05 +00:00
whitequark
f6772759c8
hdl.ir: fix port propagation between siblings, in the other direction.
2018-12-22 00:31:31 +00:00
whitequark
0df543b204
compat: do not finalize native submodules twice.
2018-12-22 00:02:31 +00:00
whitequark
a4183eba69
hdl.mem: use more informative signal naming for ports.
2018-12-21 23:55:02 +00:00
whitequark
913339c04a
hdl.ir: fix port propagation between siblings.
2018-12-21 23:53:18 +00:00
whitequark
00ef7a78d3
compat: provide verilog.convert shim.
2018-12-21 13:53:06 +00:00
whitequark
fc7da1be2d
hdl.ir: do not flatten instances or collect ports from their statements.
...
This results in absurd behavior for memories.
2018-12-21 13:52:18 +00:00
whitequark
568d3c5b7d
compat: provide Memory shim.
2018-12-21 13:15:52 +00:00
whitequark
fa2af27bb0
hdl.mem: ensure transparent read port model has correct latency.
2018-12-21 13:01:08 +00:00
whitequark
48d13e47ec
back.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 12:32:08 +00:00
whitequark
7ae7683fed
back.pysim: give numeric names to unnamed subfragments in VCD.
2018-12-21 12:29:33 +00:00
whitequark
af7db882c0
hdl.mem: use different naming for array signals.
...
It looks like [] is confusing gtkwave somehow.
2018-12-21 12:26:49 +00:00
whitequark
e58d9ec74d
hdl.mem: add simulation model for memory.
2018-12-21 11:54:32 +00:00
whitequark
a40e2cac4b
back.pysim: fix an issue with too few funclet slots.
2018-12-21 10:25:28 +00:00
whitequark
c49211c76a
hdl.mem: add tests for all error conditions.
2018-12-21 06:07:16 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
8d58cbf230
back.rtlil: more consistent prefixing for subfragment port wires.
2018-12-21 04:21:11 +00:00
whitequark
b0bd7bfaca
hdl.ir: correctly handle named output and inout ports.
2018-12-21 04:03:03 +00:00
whitequark
2b4a8510ca
back.rtlil: implement memories.
2018-12-21 01:55:59 +00:00
whitequark
6d9a6b5d84
hdl.mem: implement memories.
2018-12-21 01:53:32 +00:00
whitequark
6672ab2e3f
back.rtlil: explicitly pad constants with zeroes.
...
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
2018-12-21 01:51:18 +00:00
whitequark
221f108fbe
back.rtlil: fix translation of Cat.
2018-12-21 01:48:02 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
8cc900c4ef
setup: update pyvcd dependency, for var_type="string".
2018-12-19 17:17:25 +00:00
whitequark
0f2c7e7161
compat: import genlib.record from Migen.
2018-12-18 20:04:22 +00:00
whitequark
a90748303c
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
2018-12-18 20:03:32 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
7341d0d7ef
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
2018-12-18 16:13:29 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
51a92bc870
Travis: cache Yosys installation explicitly.
2018-12-18 00:42:14 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
de6c12af77
Travis: build and cache Yosys.
2018-12-17 17:21:42 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
8c4de99c0d
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
2018-12-17 17:21:29 +00:00
whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
