When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.
Fixes#456.
Supersedes #457.
Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.
Fixes#419.
