Irides
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b1eba5fd82
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vendor.xilinx: support setting options on synth_design
Closes #606.
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2021-12-11 12:09:09 +00:00 |
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whitequark
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fd7d01ef10
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back.rtlil,cli: allow suppressing generation of src attributes.
Fixes #572.
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2021-12-11 11:38:40 +00:00 |
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whitequark
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66295fa388
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sim.pysim: refuse to write VCD files with whitespace in signal names.
Closes #595.
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2021-12-11 11:12:25 +00:00 |
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whitequark
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b452e0e871
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hdl.ast: support division and modulo with negative divisor.
Fixes #621.
This commit bumps the Yosys version requirement to >=0.10.
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2021-12-11 10:25:48 +00:00 |
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whitequark
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25573c5eff
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back.rtlil: extend unsigned operand of binop if another is signed.
Fixes #580.
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2021-12-11 10:25:48 +00:00 |
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whitequark
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44b8bd29af
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hdl.ast: warn on bare integer value used in Cat()/Repl().
Fixes #639.
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2021-12-11 08:18:33 +00:00 |
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whitequark
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de7c9acb19
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_utils: don't crash trying to flatten() strings.
Fixes #614.
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2021-12-11 07:39:35 +00:00 |
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whitequark
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909a3b8be7
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Rename nMigen to Amaranth HDL.
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2021-12-10 10:34:13 +00:00 |
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