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7 commits

Author SHA1 Message Date
whitequark f60ceb349b vendor.xilinx_{spartan6,7series}: speedgrade→speed. 
For consistency with ECP5.
 2019-06-25 15:51:52 +00:00
whitequark 3fc5f170e6 vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. 
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
 2019-06-17 15:47:56 +00:00
whitequark 2a8e7bc6f2 vendor.xilinx_{7series,spartan6}: cleanup. NFC. 
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
 2019-06-17 15:47:56 +00:00
whitequark 8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. 
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
 2019-06-17 15:47:56 +00:00
Jean-François Nguyen 412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. 2019-06-13 15:13:31 +00:00
whitequark efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
Jean-François Nguyen d5ba26b174 vendor.xilinx_spartan6: implement. 2019-06-07 08:58:41 +00:00