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Author SHA1 Message Date
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark 3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00
whitequark c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
 2019-05-15 06:44:50 +00:00
whitequark 39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. 2019-05-13 15:34:13 +00:00
whitequark 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 040811c2e5 hdl.ir: add an API for retrieving generated values, like FSM signal. 
This is useful for tests.
 2018-12-26 12:35:35 +00:00
whitequark 68dae9f50e hdl.ir: flatten hierarchy based on memory accesses, too. 2018-12-22 21:43:46 +00:00
whitequark f6772759c8 hdl.ir: fix port propagation between siblings, in the other direction. 2018-12-22 00:31:31 +00:00
whitequark 913339c04a hdl.ir: fix port propagation between siblings. 2018-12-21 23:53:18 +00:00
whitequark b0bd7bfaca hdl.ir: correctly handle named output and inout ports. 2018-12-21 04:03:03 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark c6e7a93717 hdl: appropriately rename tests. NFC. 2018-12-15 16:13:53 +00:00
Renamed from nmigen/test/test_fhdl_ir.py (Browse further)