4 commits

Author	SHA1	Message	Date
whitequark	fdb0c5a6bc	hdl.ir: call back from Fragment.prepare if a clock domain is missing. ... See #57.	2019-08-03 14:54:20 +00:00
whitequark	7890c0adc8	test.compat: reenable tests converting to Verilog.	2019-01-26 15:29:09 +00:00
whitequark	4948162f33	hdl.ir: rename .get_fragment() to .elaborate(). ... Closes #9.	2019-01-26 02:31:12 +00:00
whitequark	00ef7a78d3	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00