58 lines
3.4 KiB
Markdown
58 lines
3.4 KiB
Markdown
# Amaranth HDL (previously nMigen)
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The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language, as well as [evaluation board definitions][amaranth-boards], a [System on Chip toolkit][amaranth-soc], and more. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components.
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The Amaranth toolchain consists of the Amaranth hardware definition language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer’s choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow.
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[amaranth-boards]: https://github.com/amaranth-lang/amaranth-boards
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[amaranth-soc]: https://github.com/amaranth-lang/amaranth-soc
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The development of Amaranth has been supported by [LambdaConcept][], [ChipEleven][], and [Chipflow][].
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[yosys]: https://yosyshq.net/yosys/
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[lambdaconcept]: http://lambdaconcept.com/
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[chipeleven]: https://chipeleven.com/
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[chipflow]: https://chipflow.io/
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## Introduction
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See the [Introduction](https://amaranth-lang.org/docs/amaranth/latest/intro.html) section of the documentation.
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## Installation
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See the [Installation](https://amaranth-lang.org/docs/amaranth/latest/install.html) section of the documentation.
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## Usage
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See the [Language guide](https://amaranth-lang.org/docs/amaranth/latest/guide.html) section of the documentation.
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## Platform support
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Amaranth can be used to target any FPGA or ASIC process that accepts behavioral Verilog-2001 as input. It also offers extended support for many FPGA families, providing toolchain integration, abstractions for device-specific primitives, and more. Specifically:
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* Lattice iCE40 (toolchains: **Yosys+nextpnr**, LSE-iCECube2, Synplify-iCECube2);
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* Lattice MachXO2, MachXO3L (toolchains: **Yosys+nextpnr**, Diamond);
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* Lattice ECP5 (toolchains: **Yosys+nextpnr**, Diamond);
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* Lattice Nexus (toolchains: **Yosys+nextpnr**, Radiant);
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* AMD Virtex, Virtex E, Spartan 2, Spartan 2E (toolchains: ISE);
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* AMD Virtex II, Virtex II Pro (toolchains: ISE);
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* AMD Spartan 3, Spartan 3E, Spartan 3A, Spartan 3AN, Spartan 3A DSP (toolchains: ISE);
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* AMD Virtex 4, Virtex 5, Virtex 6 (toolchains: ISE);
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* AMD Spartan 6 (toolchains: ISE);
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* AMD 7-series (toolchains: Vivado, ISE);
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* AMD UltraScale, UltraScale+ (toolchains: Vivado);
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* Altera (toolchains: Quartus);
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* Quicklogic EOS S3 (toolchains: **Yosys+VPR**).
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FOSS toolchains are listed in **bold**.
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## Community
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Amaranth has a dedicated IRC channel, [#amaranth-lang at libera.chat](https://web.libera.chat/#amaranth-lang), which is _bridged_[^1] to Matrix at [#amaranth-lang:matrix.org](https://matrix.to/#/#amaranth-lang:matrix.org). Feel free to join to ask questions about using Amaranth or discuss ongoing development of Amaranth and its related projects.
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[^1]: The same messages appear on IRC and on Matrix, and one can participate in the discussion equally using either communication system.
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## License
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Amaranth is released under the [two-clause BSD license](LICENSE.txt). You are permitted to use Amaranth for open-source and proprietary designs provided that the copyright notice in the license file is reproduced.
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