whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. ... Fixes #8.		2019-01-14 15:38:16 +00:00
..
__init__.py	fhdl.ast: add tests for most logic.	2018-12-13 02:06:55 +00:00
test_hdl_ast.py	hdl.ast: Cat.{operands→parts}	2018-12-18 19:15:50 +00:00
test_hdl_cd.py	hdl.mem: add tests for all error conditions.	2018-12-21 06:07:16 +00:00
test_hdl_dsl.py	hdl: make ClockSignal and ResetSignal usable on LHS.	2019-01-14 15:38:16 +00:00
test_hdl_ir.py	hdl.ir: add an API for retrieving generated values, like FSM signal.	2018-12-26 12:35:35 +00:00
test_hdl_mem.py	hdl.mem: add DummyPort, for testing and verification.	2019-01-01 03:08:10 +00:00
test_hdl_rec.py	hdl.rec: include record name in error message.	2019-01-01 03:39:12 +00:00
test_hdl_xfrm.py	hdl: make ClockSignal and ResetSignal usable on LHS.	2019-01-14 15:38:16 +00:00
test_lib_cdc.py	lib.cdc: fix tests to actually run.	2018-12-29 15:02:44 +00:00
test_lib_coding.py	lib.coding: fix tests to actually run, and fix code to fix tests.	2018-12-27 21:45:55 +00:00
test_sim.py	back.pysim: handle non-driven, non-port signals.	2019-01-13 08:31:38 +00:00
tools.py	hdl.dsl: cases wider than switch test value are unreachable.	2019-01-13 08:51:49 +00:00