whitequark 2566747061 compat.fhdl.structure: fix Case().makedefault(). ... Fixes #100.		2019-06-13 03:56:57 +00:00
..
__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
conv_output.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
module.py	compat.fhdl.module: silence "unused elaboratable" warnings.	2019-06-04 13:09:36 +00:00
specials.py	compat.fhdl.specials: fix platform lowering for TSTriple again.	2019-06-04 13:03:56 +00:00
structure.py	compat.fhdl.structure: fix Case().makedefault().	2019-06-13 03:56:57 +00:00
verilog.py	test.compat: reenable tests converting to Verilog.	2019-01-26 15:29:09 +00:00