..
compat
lib.fifo: adjust properties to have consistent naming.
2019-09-13 12:33:41 +00:00
__init__.py
hdl.ir: detect elaboratables that are created but not used.
2019-04-21 08:52:57 +00:00
test_build_dsl.py
build.dsl: allow both str and int resource attributes.
2019-08-30 08:35:52 +00:00
test_build_res.py
hdl.ast: rename nbits
to width
.
2019-09-20 15:36:25 +00:00
test_compat.py
compat.fhdl.module: CompatModule should be elaboratable.
2019-06-04 11:11:31 +00:00
test_examples.py
test.test_examples: Convert pathlib-specific class to string.
2019-08-20 00:54:10 +00:00
test_hdl_ast.py
hdl.ast: rename nbits
to width
.
2019-09-20 15:36:25 +00:00
test_hdl_cd.py
hdl.cd: add negedge clock domains.
2019-08-31 22:05:48 +00:00
test_hdl_dsl.py
hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
2019-09-16 19:22:12 +00:00
test_hdl_ir.py
build.plat, hdl.ir: coordinate missing domain creation.
2019-08-19 22:52:01 +00:00
test_hdl_mem.py
hdl.mem: use 1 as reset value for ReadPort.en.
2019-09-20 19:51:13 +00:00
test_hdl_rec.py
hdl.rec: respect modifications to signals in Record.like().
2019-07-08 10:59:15 +00:00
test_hdl_xfrm.py
hdl.xfrm: lower resets in DomainLowerer as well.
2019-08-19 21:44:30 +00:00
test_lib_cdc.py
Clean up imports.
2019-06-04 08:18:50 +00:00
test_lib_coding.py
formal→asserts
2019-08-19 20:23:24 +00:00
test_lib_fifo.py
test.test_lib_fifo: fix typo.
2019-09-20 11:53:05 +00:00
test_lib_io.py
Clean up imports.
2019-06-04 08:18:50 +00:00
test_sim.py
hdl.mem: use 1 as reset value for ReadPort.en.
2019-09-20 19:51:13 +00:00
tools.py
_toolchain,build.plat,vendor.*: add required_tools list and checks.
2019-08-31 00:05:47 +00:00