whitequark 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. ... Otherwise the following code fails to compile: index = Signal(1) array = Array(range(2)) with m.If(0 == array[index]): m.d.sync += index.eq(0) Fixes #51.		2019-04-21 06:43:31 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: support async reset.	2019-01-26 18:07:43 +00:00
rtlil.py	back.rtlil: only expand legalized values in Array/Part context on RHS.	2019-04-21 06:43:31 +00:00
verilog.py	back.verilog: better error message if Yosys is not found.	2019-01-13 08:10:23 +00:00