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amaranth/nmigen
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whitequark 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. 
Otherwise the following code fails to compile:

    index = Signal(1)
    array = Array(range(2))
    with m.If(0 == array[index]):
        m.d.sync += index.eq(0)

Fixes #51.
2019-04-21 06:43:31 +00:00
..
back back.rtlil: only expand legalized values in Array/Part context on RHS. 2019-04-21 06:43:31 +00:00
compat lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
hdl hdl.rec: implement Record.connect. 2019-04-21 06:37:08 +00:00
lib lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
test hdl.rec: implement Record.connect. 2019-04-21 06:37:08 +00:00
__init__.py lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
cli.py hdl.ir: rename .get_fragment() to .elaborate(). 2019-01-26 02:31:12 +00:00
formal.py formal: extract from toplevel module. 2019-01-17 01:43:07 +00:00
tools.py compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
tracer.py tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00