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compat
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compat: suppress deprecation warnings that are internal or during test.
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2019-01-26 15:43:00 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.{dsl,res}: allow removing attributes from subsignals.
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2019-07-08 10:42:10 +00:00 |
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test_build_res.py
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build.res: detect physical conflicts earlier.
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2019-07-03 15:07:44 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_examples.py
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test: generate examples to verilog as part of unit tests.
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2019-07-08 10:12:26 +00:00 |
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test_hdl_ast.py
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hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
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2019-07-08 10:26:49 +00:00 |
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test_hdl_cd.py
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hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
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2019-07-08 10:26:49 +00:00 |
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test_hdl_dsl.py
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hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
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2019-07-08 10:26:49 +00:00 |
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test_hdl_ir.py
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hdl.ir, back.rtlil: allow specifying attributes on instances.
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2019-06-28 04:14:38 +00:00 |
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test_hdl_mem.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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test_hdl_rec.py
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hdl.rec: respect modifications to signals in Record.like().
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2019-07-08 10:59:15 +00:00 |
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test_hdl_xfrm.py
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hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
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2019-07-08 10:26:49 +00:00 |
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test_lib_cdc.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_coding.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_fifo.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
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2019-07-01 19:56:49 +00:00 |
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tools.py
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hdl.ir: rename .get_fragment() to .elaborate().
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2019-01-26 02:31:12 +00:00 |
