..
compat
compat: suppress deprecation warnings that are internal or during test.
2019-01-26 15:43:00 +00:00
__init__.py
hdl.ir: detect elaboratables that are created but not used.
2019-04-21 08:52:57 +00:00
test_build_dsl.py
build.{dsl,res}: allow removing attributes from subsignals.
2019-07-08 10:42:10 +00:00
test_build_res.py
build.res: detect physical conflicts earlier.
2019-07-03 15:07:44 +00:00
test_compat.py
compat.fhdl.module: CompatModule should be elaboratable.
2019-06-04 11:11:31 +00:00
test_examples.py
test: generate examples to verilog as part of unit tests.
2019-07-08 10:12:26 +00:00
test_hdl_ast.py
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
2019-07-08 10:26:49 +00:00
test_hdl_cd.py
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
2019-07-08 10:26:49 +00:00
test_hdl_dsl.py
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
2019-07-08 10:26:49 +00:00
test_hdl_ir.py
hdl.ir, back.rtlil: allow specifying attributes on instances.
2019-06-28 04:14:38 +00:00
test_hdl_mem.py
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
2019-07-01 19:56:49 +00:00
test_hdl_rec.py
hdl.rec: implement slicing by component names.
2019-07-02 17:46:53 +00:00
test_hdl_xfrm.py
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
2019-07-08 10:26:49 +00:00
test_lib_cdc.py
Clean up imports.
2019-06-04 08:18:50 +00:00
test_lib_coding.py
Clean up imports.
2019-06-04 08:18:50 +00:00
test_lib_fifo.py
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
2019-07-01 19:56:49 +00:00
test_lib_io.py
Clean up imports.
2019-06-04 08:18:50 +00:00
test_sim.py
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
2019-07-01 19:56:49 +00:00
tools.py
hdl.ir: rename .get_fragment() to .elaborate().
2019-01-26 02:31:12 +00:00