whitequark 15e8dfe532 vendor.xilinx_spartan_3_6: do not use retiming by default. ... This was added in b404d603, probably by mistake, and is certainly wrong given that we do not (yet) correctly mark CDC FFs.		2019-08-04 13:48:33 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ecp5.py	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
lattice_ice40.py	vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.	2019-08-04 00:30:50 +00:00
xilinx_7series.py	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
xilinx_spartan_3_6.py	vendor.xilinx_spartan_3_6: do not use retiming by default.	2019-08-04 13:48:33 +00:00