whitequark 1aeb11d7e3 hdl.mem: simplify. NFC.		2019-09-23 11:16:29 +00:00
..
__init__.py	hdl.xfrm: CEInserter→EnableInserter.	2019-08-12 13:39:26 +00:00
ast.py	hdl.ast: make Signal(name=) a keyword-only argument.	2019-09-23 11:08:43 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
ir.py	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
mem.py	hdl.mem: simplify. NFC.	2019-09-23 11:16:29 +00:00
rec.py	hdl.rec: fix using Enum subclass as shape if direction is specified.	2019-09-22 17:23:32 +00:00
xfrm.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00