whitequark 6b843b5be6 hdl.rec: implement slicing by component names. ... Fixes #121.		2019-07-02 17:46:53 +00:00
..
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
ast.py	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
ir.py	hdl.ir, back.rtlil: allow specifying attributes on instances.	2019-06-28 04:14:38 +00:00
mem.py	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
rec.py	hdl.rec: implement slicing by component names.	2019-07-02 17:46:53 +00:00
xfrm.py	hdl.ir, back.rtlil: allow specifying attributes on instances.	2019-06-28 04:14:38 +00:00