whitequark 29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports. ... Fixes #248.		2019-10-13 03:39:56 +00:00
..
__init__.py	hdl.ast: add an explicit Shape class, included in prelude.	2019-10-11 12:52:41 +00:00
ast.py	hdl.ast: rename Slice.end back to Slice.stop.	2019-10-12 22:40:48 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	_tools: extract most utility methods to a private package.	2019-10-12 22:40:48 +00:00
ir.py	hdl.ir: allow ClockSignal and ResetSignal in ports.	2019-10-13 03:39:56 +00:00
mem.py	hdl.ast: deprecate Signal.{range,enum}.	2019-10-11 13:07:42 +00:00
rec.py	_tools: extract most utility methods to a private package.	2019-10-12 22:40:48 +00:00
xfrm.py	hdl.ir: allow ClockSignal and ResetSignal in ports.	2019-10-13 03:39:56 +00:00