whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). ... Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.		2019-08-19 19:49:51 +00:00
..
__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
conv_output.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
decorators.py	compat.fhdl.decorators: avoid using deprecated NativeCEInserter.	2019-08-18 16:27:11 +00:00
module.py	compat.fhdl.module: fix finalization of transformed compat submodules.	2019-08-08 07:45:34 +00:00
specials.py	compat.fhdl.specials: track changes in build.plat.	2019-08-03 22:52:34 +00:00
structure.py	compat.fhdl.structure: fix If/Elif/Else after 32446831.	2019-07-03 13:19:15 +00:00
verilog.py	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00