whitequark 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. ... Currently only done for Synopsys based toolchains (i.e. not nextpnr). Refs #88.		2019-09-11 23:35:43 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ecp5.py	build.plat,vendor: allow clock constraints on arbitrary signals.	2019-09-11 23:35:43 +00:00
lattice_ice40.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00
xilinx_7series.py	build.plat,vendor: allow clock constraints on arbitrary signals.	2019-09-11 23:35:43 +00:00
xilinx_spartan_3_6.py	build.plat,vendor: allow clock constraints on arbitrary signals.	2019-09-11 23:35:43 +00:00