whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. ... Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys and when it doesn't, it causes Yosys to produce invalid Verilog. Using a dummy wire is always safe and is not a major readability issue as this is a rare corner case. (It is not trivial to shorten the RHS in this case, because during expansion of an ArrayProxy, match_shape() could be called in a context far from the RHS handling logic.)		2019-08-04 00:12:08 +00:00
..
back	back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.	2019-08-04 00:12:08 +00:00
build	build.run: use keyword-only arguments where appropriate.	2019-08-03 22:52:58 +00:00
compat	compat.fhdl.specials: track changes in build.plat.	2019-08-03 22:52:34 +00:00
hdl	hdl.dsl: reword m.If(~True) warning to be more clear.	2019-08-03 18:52:24 +00:00
lib	lib.fifo: fix typo.	2019-07-15 14:12:33 +00:00
test	hdl.dsl: reword m.If(~True) warning to be more clear.	2019-08-03 18:52:24 +00:00
vendor	vendor.lattice_ice40: add missing signal indexing.	2019-08-03 22:59:33 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: add PyPy support to get_var_name().	2019-07-09 07:29:01 +00:00