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awygle 2f8669cad6
lib.cdc: extract AsyncFFSynchronizer. 
In some cases, it is necessary to synchronize a reset-like signal but
a new clock domain is not desirable. To address these cases, extract
the implementation of ResetSynchronizer into AsyncFFSynchronizer,
and replace ResetSynchronizer with a thin wrapper around it.
2020-03-08 21:37:40 +00:00
..
__init__.py vendor.fpga.lattice_ice40: implement. 2019-06-01 16:47:01 +00:00
intel.py lib.cdc: extract AsyncFFSynchronizer. 2020-03-08 21:37:40 +00:00
lattice_ecp5.py build.res,vendor: place clock constraint on port, not net, if possible. 2020-02-06 23:37:15 +00:00
lattice_ice40.py build.res,vendor: place clock constraint on port, not net, if possible. 2020-02-06 23:37:15 +00:00
lattice_machxo2.py build.res,vendor: place clock constraint on port, not net, if possible. 2020-02-06 23:37:15 +00:00
xilinx_7series.py lib.cdc: extract AsyncFFSynchronizer. 2020-03-08 21:37:40 +00:00
xilinx_spartan_3_6.py lib.cdc: extract AsyncFFSynchronizer. 2020-03-08 21:37:40 +00:00
xilinx_ultrascale.py lib.cdc: extract AsyncFFSynchronizer. 2020-03-08 21:37:40 +00:00