whitequark 300d47ca2e back.pysim: override ResetSynchronizer implementation. ... This was rewritten to use Yosys cells in 779f3ee9 to avoid leaking the interior clock domain, but the simulator doesn't understand Yosys cells. So, use the old implementation in the simulator.		2019-06-28 07:49:14 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: override ResetSynchronizer implementation.	2019-06-28 07:49:14 +00:00
rtlil.py	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00