whitequark 300d47ca2e back.pysim: override ResetSynchronizer implementation. ... This was rewritten to use Yosys cells in 779f3ee9 to avoid leaking the interior clock domain, but the simulator doesn't understand Yosys cells. So, use the old implementation in the simulator.		2019-06-28 07:49:14 +00:00
..
back	back.pysim: override ResetSynchronizer implementation.	2019-06-28 07:49:14 +00:00
build	build.plat: fix dedent overrides.	2019-06-28 06:52:52 +00:00
compat	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
hdl	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
lib	lib.cdc: avoid interior clock domains in ResetSynchronizer.	2019-06-28 07:34:10 +00:00
test	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
vendor	vendor.lattice_ice40: fix instance of negedge FF due to a typo.	2019-06-28 07:05:20 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00