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amaranth/nmigen/compat/fhdl
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whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
2019-06-28 04:37:08 +00:00
..
__init__.py compat.fhdl.bitcontainer: import/wrap Migen code. 2018-12-12 15:22:34 +00:00
bitcontainer.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
conv_output.py compat: provide verilog.convert shim. 2018-12-21 13:53:06 +00:00
module.py compat.fhdl.module: silence "unused elaboratable" warnings. 2019-06-04 13:09:36 +00:00
specials.py compat.fhdl.specials: fix platform lowering for TSTriple again. 2019-06-04 13:03:56 +00:00
structure.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
verilog.py test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00