whitequark 892cff059b vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks. ... If the clock signal is not a top-level port and has aliases, it can be optimized out, and then the constraint will no longer apply. To prevent this, make sure the constrained signal is preferred over any aliases by using the `keep` attribute. Vivado does not parse attributes like (* keep = 32'd1 *) as valid even though, AFAICT, they are equivalent to (* keep = 1 *) or simply (* keep *) per IEEE 1364. To work around this, use the solution we currently use for Quartus, which is `write_verilog -decimal`. Fixes #373.		2020-05-20 04:58:03 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.	2020-05-20 04:58:03 +00:00
lattice_ecp5.py	plat, vendor: systematically escape net and file names in Tcl.	2020-05-02 10:41:18 +00:00
lattice_ice40.py	plat, vendor: systematically escape net and file names in Tcl.	2020-05-02 10:41:18 +00:00
lattice_machxo2.py	vendor.lattice_machxo2: generate binary bitstreams.	2020-05-08 04:42:21 +00:00
xilinx_7series.py	vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.	2020-05-20 04:58:03 +00:00
xilinx_spartan_3_6.py	vendor: fix typo async_ff_sync	2020-03-15 11:34:52 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.	2020-05-20 04:58:03 +00:00