whitequark 3d7214cb70 vendor.xilinx_spartan_3_6: reconsider bitgen defaults. ... Previously changed in 27063a3b. I haven't realized the .bin file is the same as the .bit file without a small header. That means generating it is free and it's just easier to let programming tools to be able to always rely on its existence.		2019-08-04 23:28:09 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ecp5.py	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
lattice_ice40.py	vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress.	2019-08-04 14:18:49 +00:00
xilinx_7series.py	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
xilinx_spartan_3_6.py	vendor.xilinx_spartan_3_6: reconsider bitgen defaults.	2019-08-04 23:28:09 +00:00