whitequark 3e59d857e1 back.pysim: use bare ints for signal values (-5% runtime).		2018-12-14 03:05:57 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: use bare ints for signal values (-5% runtime).	2018-12-14 03:05:57 +00:00
rtlil.py	fhdl.ir: move Fragment prepare logic from back.rtlil.	2018-12-13 14:34:07 +00:00
verilog.py	back.verilog: remove debug code.	2018-12-13 13:42:54 +00:00