Jean-François Nguyen 412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.		2019-06-13 15:13:31 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ice40.py	Simplify code by using Signal.like(name_suffix="..") appropriately.	2019-06-12 22:28:45 +00:00
xilinx_7series.py	vendor.xilinx_7series: implement DDR I/O buffers.	2019-06-12 19:55:10 +00:00
xilinx_spartan6.py	vendor.xilinx_spartan6: implement DDR I/O buffers and inverters.	2019-06-13 15:13:31 +00:00