whitequark 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. ... On Xilinx devices, flip-flops are reset to their initial state with an internal global reset network, but this network is deasserted asynchronously to user clocks. Use BUFGCE and STARTUP to hold default clock low until after GWE is deasserted.		2019-08-04 23:28:09 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ecp5.py	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
lattice_ice40.py	vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress.	2019-08-04 14:18:49 +00:00
xilinx_7series.py	vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.	2019-08-04 23:28:09 +00:00
xilinx_spartan_3_6.py	vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.	2019-08-04 23:28:09 +00:00