whitequark 450d7efdf2 hdl.dsl: add a diagnostic for m.d.submodules += ....		2019-09-28 17:50:24 +00:00
..
__init__.py	hdl.xfrm: CEInserter→EnableInserter.	2019-08-12 13:39:26 +00:00
ast.py	hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.	2019-09-23 13:39:31 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	hdl.dsl: add a diagnostic for m.d.submodules += ....	2019-09-28 17:50:24 +00:00
ir.py	build.plat, hdl.ir: coordinate missing domain creation.	2019-08-19 22:52:01 +00:00
mem.py	hdl.mem: remove WritePort(priority=) argument.	2019-09-28 01:29:56 +00:00
rec.py	hdl.rec: fix using Enum subclass as shape if direction is specified.	2019-09-22 17:23:32 +00:00
xfrm.py	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00