4b3a068b15
This is necessary for consistency, since for transparent read ports, we currently do not support .en at all (it is fixed at 1) due to YosysHQ/yosys#760. Before this commit, changing port transparency would require adding or removing an assignment to .en, which is confusing and error-prone. Also, most read ports are always enabled, so this behavior is also convenient.
132 lines
5.1 KiB
Python
132 lines
5.1 KiB
Python
from ..hdl.ast import *
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from ..hdl.mem import *
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from .tools import *
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class MemoryTestCase(FHDLTestCase):
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def test_name(self):
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m1 = Memory(width=8, depth=4)
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self.assertEqual(m1.name, "m1")
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m2 = [Memory(width=8, depth=4)][0]
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self.assertEqual(m2.name, "$memory")
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m3 = Memory(width=8, depth=4, name="foo")
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self.assertEqual(m3.name, "foo")
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def test_geometry(self):
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m = Memory(width=8, depth=4)
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self.assertEqual(m.width, 8)
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self.assertEqual(m.depth, 4)
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def test_geometry_wrong(self):
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with self.assertRaises(TypeError,
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msg="Memory width must be a non-negative integer, not '-1'"):
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m = Memory(width=-1, depth=4)
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with self.assertRaises(TypeError,
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msg="Memory depth must be a non-negative integer, not '-1'"):
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m = Memory(width=8, depth=-1)
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def test_init(self):
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m = Memory(width=8, depth=4, init=range(4))
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self.assertEqual(m.init, [0, 1, 2, 3])
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def test_init_wrong_count(self):
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with self.assertRaises(ValueError,
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msg="Memory initialization value count exceed memory depth (8 > 4)"):
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m = Memory(width=8, depth=4, init=range(8))
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def test_init_wrong_type(self):
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with self.assertRaises(TypeError,
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msg="Memory initialization value at address 1: "
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"'str' object cannot be interpreted as an integer"):
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m = Memory(width=8, depth=4, init=[1, "0"])
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def test_read_port_transparent(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port()
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "sync")
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self.assertEqual(rdport.transparent, True)
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self.assertEqual(len(rdport.addr), 2)
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self.assertEqual(len(rdport.data), 8)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Const)
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self.assertEqual(rdport.en.value, 1)
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def test_read_port_non_transparent(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port(transparent=False)
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "sync")
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self.assertEqual(rdport.transparent, False)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Signal)
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self.assertEqual(rdport.en.reset, 1)
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def test_read_port_asynchronous(self):
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mem = Memory(width=8, depth=4)
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rdport = mem.read_port(domain="comb")
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self.assertEqual(rdport.memory, mem)
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self.assertEqual(rdport.domain, "comb")
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self.assertEqual(rdport.transparent, True)
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self.assertEqual(len(rdport.en), 1)
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self.assertIsInstance(rdport.en, Const)
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self.assertEqual(rdport.en.value, 1)
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def test_read_port_wrong(self):
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mem = Memory(width=8, depth=4)
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with self.assertRaises(ValueError,
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msg="Read port cannot be simultaneously asynchronous and non-transparent"):
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mem.read_port(domain="comb", transparent=False)
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def test_write_port(self):
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mem = Memory(width=8, depth=4)
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wrport = mem.write_port()
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self.assertEqual(wrport.memory, mem)
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self.assertEqual(wrport.domain, "sync")
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self.assertEqual(wrport.priority, 0)
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self.assertEqual(wrport.granularity, 8)
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self.assertEqual(len(wrport.addr), 2)
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self.assertEqual(len(wrport.data), 8)
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self.assertEqual(len(wrport.en), 1)
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def test_write_port_granularity(self):
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mem = Memory(width=8, depth=4)
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wrport = mem.write_port(granularity=2)
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self.assertEqual(wrport.memory, mem)
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self.assertEqual(wrport.domain, "sync")
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self.assertEqual(wrport.priority, 0)
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self.assertEqual(wrport.granularity, 2)
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self.assertEqual(len(wrport.addr), 2)
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self.assertEqual(len(wrport.data), 8)
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self.assertEqual(len(wrport.en), 4)
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def test_write_port_granularity_wrong(self):
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mem = Memory(width=8, depth=4)
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with self.assertRaises(TypeError,
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msg="Write port granularity must be a non-negative integer, not '-1'"):
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mem.write_port(granularity=-1)
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with self.assertRaises(ValueError,
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msg="Write port granularity must not be greater than memory width (10 > 8)"):
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mem.write_port(granularity=10)
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with self.assertRaises(ValueError,
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msg="Write port granularity must divide memory width evenly"):
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mem.write_port(granularity=3)
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class DummyPortTestCase(FHDLTestCase):
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def test_name(self):
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p1 = DummyPort(width=8, addr_bits=2)
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self.assertEqual(p1.addr.name, "p1_addr")
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p2 = [DummyPort(width=8, addr_bits=2)][0]
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self.assertEqual(p2.addr.name, "dummy_addr")
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p3 = DummyPort(width=8, addr_bits=2, name="foo")
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self.assertEqual(p3.addr.name, "foo_addr")
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def test_sizes(self):
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p1 = DummyPort(width=8, addr_bits=2)
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self.assertEqual(p1.addr.width, 2)
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self.assertEqual(p1.data.width, 8)
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self.assertEqual(p1.en.width, 1)
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p2 = DummyPort(width=8, addr_bits=2, granularity=2)
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self.assertEqual(p2.en.width, 4)
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